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rev. 1.6 march 2010 www.aosmd.com page 1 of 15 AOZ1031AI ezbuck? 3a synchron ous buck regulator general description the aoz1031a is a high efficiency, easy to use, 3a synchronous buck regulator. the aoz1031a works from 4.5v to 18v input voltage range, and provides up to 3a of continuous output current with an output voltage adjust- able down to 0.8v. the aoz1031a comes in a so-8 package and is rated over a -40 c to +85 c operating ambient temperature range. features z 4.5v to 18v operating input voltage range z synchronous buck: 80m internal high-side switch and 30m internal low-side sw itch with integrated schottky diode z high efficiency: up to 95% z internal soft start z output voltage adjustable to 0.8v z 3a continuous output current z fixed 600khz pwm operation z pulse skipping at light load for high efficiency over entire load range z cycle-by-cycle current limit z pre-bias start-up z short-circuit protection z thermal shutdown z so-8 package applications z point of load dc/dc converters z lcd tv z set top boxes z dvd/blu-ray players/recorders z cable modems z pcie graphics cards z telecom/networking/datacom equipment typical application figure 1. 3.3v 3a synchronous buck regulator lx vin vin vout fb pgnd en comp agnd c2, c3 22f r1 r2 c c r c c1 22f l1 4.7h aoz1031
rev. 1.6 march 2010 www.aosmd.com page 2 of 15 AOZ1031AI ordering information aos green products use reduced levels of halogens, and are also rohs compliant. please visit www.aosmd.com/web/quality/rohs_compliant.jsp for additional information. pin configuration pin description part number ambient temperature range package environmental AOZ1031AI -40c to +85c so-8 rohs compliant green product pin number pin name pin function 1 pgnd power ground. pgnd needs to be electrically connected to agnd. 2 vin supply voltage input. when vin rises above the uvlo threshold and en is logic high, the device starts up. 3 agnd analog ground. agnd is the reference point for controller section. agnd needs to be electrically connected to pgnd. 4 fb feedback input. the fb pin is used to set the output voltage via a resistive voltage divider between the output and agnd. 5 comp external loop compensation pin. c onnect a rc network between comp and agnd to compensate the control loop. 6 en enable pin. pull en to logic high to enable the device. pull en to logic low to disable the device. do not leave it open. 7, 8 lx switching node. pwm output connection to inductor. lx lx en comp 1 2 3 4 pgnd vin agnd fb so-8 (top view) 8 7 6 5
AOZ1031AI rev. 1.6 march 2010 www.aosmd.com page 3 of 15 block diagram absolute maximum ratings exceeding the absolute maximum ratings may damage the device. note: 1. devices are inherently esd s ensitive, handling precautions are required. human body model rating: 1.5k in series with 100pf. recommend operating ratings the device is not guaranteed to operate beyond the maximum operating ratings. 600khz agnd pgnd vin en fb comp lx otp internal +5v ilimit pwm control logic 5v ldo regulator uvlo & por softstart reference & bias 0.8v q1 q2 pwm comp level shifter + fet driver isen eamp 0.2v + ? + ? + ? + ? + frequency foldback comparator + ? over-voltage protection comparator 0.96v parameter rating supply voltage (v in )20v lx to agnd -0.7v to v in +0.3v lx to agnd -3v for 20 ns en to agnd -0.3v to v in +0.3v fb to agnd -0.3v to 6v comp to agnd -0.3v to 6v pgnd to agnd -0.3v to +0.3v junction temperature (t j ) +150c storage temperature (t s ) -65c to +150c esd rating (1) 2.0kv parameter rating supply voltage (v in ) 4.5v to 18v output voltage range 0.8v to v in ambient temperature (t a ) -40c to +85c package therma l resistance so-8 ( ja ) so-8 ( jc ) 87c/w 30c/w package power dissipation (p d ) @ 25c ambient so-8 1.15w
AOZ1031AI rev. 1.6 march 2010 www.aosmd.com page 4 of 15 electrical characteristics t a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified. (3) notes: 3. the device is not guaranteed to oper ate beyond the maximum operating ratings. symbol parameter conditions min. typ. max. units v in supply voltage 4.5 18 v v uvlo input under-voltage lockout threshold v in rising v in falling 4.1 3.7 v v i in supply current (quiescent) i out = 0, v fb = 1.2v, v en >1.2v 1.6 2.5 ma i off shutdown supply current v en = 0v 110 a v fb feedback voltage t a = 25c 0.788 0.8 0.812 v load regulation 0.5 % line regulation 1% i fb feedback voltage input current 200 na v en en input threshold off threshold on threshold 2 0.6 v v v hys en input hysteresis 100 mv modulator f o frequency 500 600 700 khz d max maximum duty cycle 100 % d min minimum duty cycle 9% error amplifier voltage gain 500 v / v error amplifier transconductance 200 a / v protection i lim current limit 4.0 5.0 a v ovp over-voltage protection off threhsold on threshold 960 860 mv mv over-temperature shutdown limit t j rising t j falling 150 100 c c t ss soft start interval 2.2 ms output stage high-side switch on-resistance v in = 12v v in = 5v 80 130 100 180 m m low-side switch on-resistance v in = 12v v in = 5v 30 56 36 70 m m
AOZ1031AI rev. 1.6 march 2010 www.aosmd.com page 5 of 15 typical performance characteristics circuit of figure 1. t a = 25c, v in = v en = 12v, v out = 3.3v unless otherwise specified. light load (dcm) operation 1us/div start up to full load 1ms/div 50% to 100% load transient 100us/div full load (ccm) operation 1us/div short circuit protection 4ms/div short circuit recovery 10ms/div
AOZ1031AI rev. 1.6 march 2010 www.aosmd.com page 6 of 15 efficiency thermal derating AOZ1031AI efficiency 100 90 80 70 60 50 40 30 20 10 0 0 0.5 1.0 1.5 2.0 2.5 3.0 i out (a) 0 0.5 1.0 1.5 2.0 2.5 3.0 i out (a) efficiency (%) 100 90 80 70 60 50 40 30 20 10 0 efficiency (%) efficiency (v in = 12v) vs. load current efficiency (v in = 5v) vs. load current v o = 1.2v v o = 1.8v v o = 3.3v v o = 5v v o = 1.2v v o = 1.8v v o = 3.3v derating curves at 5v/6v input ambient temperature (t a ) output current (i o ) derating curves at 12v input 1.2v, 1.8v output 3.3v output thermal de-rating curves for so-8 package part under typical input and output condition based on the evaluation board. 25 c ambient temperature and natural convection (air speed < 50lfm) unless otherwise specified. 5 4 3 2 1 0 25 35 45 55 65 75 85 ambient temperature (t a ) output current (i o ) 1.2v, 1.8v, 3.3v, 5.0v output 5 4 3 2 1 0 25 35 45 55 65 75 85
AOZ1031AI rev. 1.6 march 2010 www.aosmd.com page 7 of 15 detailed description the aoz1031a is a current-mode step down regulator with integrated high-side pm os switch and a low-side nmos switch. it operates from a 4.5v to 18v input volt- age range and supplies up to 3a of load current. the duty cycle can be adjusted from 6% to 100% allowing a wide range of output voltage. features include enable control, power-on reset, input under voltage lockout, output over voltage protection, active high power good state, fixed internal soft-start and thermal shut down. the aoz1031a is available in so-8 package. enable and soft start the aoz1031a has internal soft start feature to limit in-rush current and ensure the output voltage ramps up smoothly to regulation voltage. a soft start process begins when the input voltage rises to 4.1v and voltage on en pin is high. in soft st art process, the output volt- age is ramped to regulation voltage in typically 2.2ms. the 2.2ms soft start time is set internally. the en pin of the aoz1031a is active high. connect the en pin to vin if enable function is not used. pull it to ground will disable the aoz1031 a. do not leave it open. the voltage on en pin must be above 2v to enable the aoz1031a. when voltage on en pin falls below 0.6v, the aoz1031a is disabled. if an application circuit requires the aoz1031a to be disabled, an open drain or open col- lector circuit should be used to interface to en pin. steady-state operation under steady-state conditions, the converter operates in fixed frequency and continuous-conduction mode (ccm). the aoz1031a integrates an internal p-mosfet as the high-side switch. inductor current is sensed by amplifying the voltage drop across the drain to source of the high side power mosfet. output voltage is divided down by the external voltage divider at the fb pin. the difference of the fb pin voltage and reference is amplified by the internal transconductance error amplifier. the error volt- age, which shows on the comp pin, is compared against the current signal, which is sum of inductor current signal and ramp compensation signal, at pwm comparator input. if the current signal is less than the error voltage, the internal high-side switch is on. the inductor current flows from the input through the inductor to the output. when the current signal exceeds the error voltage, the high-side switch is off. the inductor current is freewheel- ing through the internal low- side n-mosfet switch to output. the internal adaptive fet driver guarantees no turn on overlap of both high-side and low-side switch. comparing with regulators using freewheeling schottky diodes, the aoz1031a uses freewheeling nmosfet to realize synchronous rectification. it greatly improves the converter efficiency and reduces power loss in the low-side switch. the aoz1031a will en ter the discontin uous conduction mode at light load. several pulses may be skipped in between switching cycles at very light load, it further improving light load efficiency. the aoz1031a uses a p-channel mosfet as the high-side switch. it saves the bootstrap capacitor nor- mally seen in a circuit which is using an nmos switch. it allows 100% turn-on of the high-side switch to achieve linear regulation mode of operation. the minimum volt- age drop from v in to v o is the load current times dc resistance of mosfet plus dc resistance of buck induc- tor. it can be calculated by equation below: where; v o_max is the maximum output voltage;, v in is the input voltage from 4.5v to 18v, i o is the output current from 0a to 3a, and r ds(on) is the on resistance of in ternal mosfet. the value is between 97m and 200m depending on input voltage and junction temperature. switching frequency the aoz1031a switching frequency is fixed and set by an internal oscillator. the practical switching frequency could range from 500khz to 700khz due to device varia- tion. output voltage programming output voltage can be set by feeding back the output to the fb pin by using a resistor divider network. in the application circuit shown in figure 1. the resistor divider network includes r 1 and r 2 . usually, a design is started by picking a fixed r 2 value and calculating the required r1 with equation below. some standard value of r 1 , r 2 and most used output voltage values are listed in table 1 on the next page. v o_max v in i o r ds on () ? = v o 0.8 1 r 1 r 2 ------ - + ?? ?? ?? =
AOZ1031AI rev. 1.6 march 2010 www.aosmd.com page 8 of 15 table 1. the combination of r 1 and r 2 should be large enough to avoid drawing excessive current from the output, which will cause power loss. since the switch duty cycle can be as high as 100%, the maximum output voltage can be set as high as the input voltage minus the voltage drop on upper pmos and inductor. protection features the aoz1031a has multiple protection features to pre- vent system circuit damage under abnormal conditions. over current protection (ocp) the sensed inductor current si gnal is also used for over current protection. since the aoz1031a employs peak current mode control, the comp pin voltage is propor- tional to the peak inductor current. the comp pin volt- age is limited to be between 0.4v and 2.5v internally. the peak inductor current is automatically limited cycle by cycle. when the output is shorted to ground under fault condi- tions, the inductor current decays very slow during a switching cycle because of v o =0v. to prevent cata- strophic failure, aoz1031a detects the duration the over- current condition occurs. if the over-current condition occurs for certain period, aoz1013a totally turns off for a period of time, then restarts. if the fault is still there, then the chip will be off again. the converter will init iate a soft start once the over-current condition disappears. power-on reset (por) a power-on reset circuit monitors the input voltage. when the input voltage exceeds 4.1v , the converter starts oper- ation. when input voltage falls below 3.7v, the converter will be shut down. thermal protection an internal temperature sensor monitors the junction temperature. it shuts down the internal control circuit and high side pmos if the junction temperature exceeds 150 c. the regulator will restar t automatically under the control of soft-start circuit when the junction temperature decreases to 100 c. application information the basic aoz1031a applicat ion circuit is show in figure 1. component selection is explained below. input capacitor the input capacitor must be connected to the v in pin and pgnd pin of aoz1031a to maintain steady input voltage and filter out the pulsing input current. the voltage rating of input capacitor must be greater than maximum input voltage plus ripple voltage. the input ripple voltage can be approximated by equa- tion below: since the input current is discontinuous in a buck con- verter, the current stress on the input capacitor is another concern when selecting the capacitor. for a buck circuit, the rms value of input capacitor current can be calcu- lated by: if we let m equal the conversion ratio: the relation between the input capacitor rms current and voltage conversion ratio is calculated and shown in figure 2 on the next page. it can be seen that when v o is half of v in , c in is under the worst current stress. the worst current stress on c in is 0.5 x i o . vo (v) r1 (k ) r2 (k ) 0.8 1.0 open 1.2 4.99 10 1.5 10 11.5 1.8 12.7 10.2 2.5 21.5 10 3.3 31.1 10 5.0 52.3 10 v in i o fc in ----------------- 1 v o v in -------- - ? ?? ?? ?? v o v in -------- - = i cin_rms i o v o v in -------- - 1 v o v in -------- - ? ?? ?? ?? = v o v in -------- - m =
AOZ1031AI rev. 1.6 march 2010 www.aosmd.com page 9 of 15 figure 2. i cin vs. voltage conversion ratio for reliable operation and best performance, the input capacitors must have current rating higher than i cin_rms at worst operating conditions. ceramic capacitors are preferred for input capacitors because of their low esr and high current rating. depending on the application cir- cuits, other low esr tantalum capacitor may also be used. when selecting cerami c capacitors, x5r or x7r type dielectric ceramic capacitors should be used for their better temperature and voltage characteristics. note that the ripple current rating from capacitor manufactures are based on certain amount of life time. further de-rating may be necessary in practical design. inductor the inductor is used to supply constant current to output when it is driven by a swit ching voltage. for given input and output voltage, inductance and switching frequency together decide the inductor ripple current, which is: the peak inductor current is: high inductance gives low inductor ripple current but requires larger size inductor to avoid saturation. low rip- ple current reduces inductor core losses. it also reduces rms current through inductor and switches, which results in less conduction lo ss. usually, peak to peak rip- ple current on inductor is designed to be 20% to 30% of output current. when selecting the inductor, ma ke sure it is able to han- dle the peak current without saturation even at the high- est operating temperature. the inductor takes the highest current in a buck circuit. the conduction loss on inductor need to be checked for thermal and efficiency requirements. surface mount inductors in different shape and styles are available from coilcraft, elytone and murata. shielded inductors are small and radiate less emi noise. but they cost more than unshielded inductors. the choice depends on emi requirement, price and size. output capacitor the output capacitor is select ed based on the dc output voltage rating, output ripple voltage specification and rip- ple current rating. the selected output capacito r must have a higher rated voltage specification than the maximum desired output voltage including ripple. de-rating needs to be consid- ered for long term reliability. output ripple voltage specif ication is another important factor for selecting the outp ut capacitor. in a buck con- verter circuit, output ripple voltage is determined by inductor value, switching frequency, output capacitor value and esr. it can be calculated by the equation below: where; c o is output capacitor value, and esr co is the equivalent series resistor of output capacitor. when low esr ceramic capacitor is used as output capacitor, the impedance of the capacitor at the switching frequency dominates. output ripple is mainly caused by capacitor value and inductor ripple current. the output ripple voltage calculation can be simplified to: if the impedance of esr at switching frequency domi- nates, the output ripple voltage is mainly decided by capacitor esr and inductor ripple current. the output rip- ple voltage calculation can be further simplified to: for lower output ripple voltage across the entire operat- ing temperature range, x5r or x7r dielectric type of ceramic, or other low esr tantalum are recommended to be used as output capacitors. 0 0.1 0.2 0.3 0.4 0.5 0 0.5 1 m i cin_rms (m) i o i l v o fl ---------- - 1 v o v in -------- - ? ?? ?? ?? = i lpeak i o i l 2 -------- + = v o i l esr co 1 8 fc o ------------------------- + ?? ?? = v o i l 1 8 fc o ------------------------- = v o i l esr co =
AOZ1031AI rev. 1.6 march 2010 www.aosmd.com page 10 of 15 in a buck converter, output capacitor current is continu- ous. the rms current of output capacitor is decided by the peak to peak inductor ripple current. it can be calcu- lated by: usually, the ripple current rating of the output capacitor is a smaller issue because of the low current stress. when the buck inductor is selected to be very small and induc- tor ripple current is high, ou tput capacitor could be over- stressed. loop compensation the aoz1031a employs peak current mode control for easy use and fast transient response. peak current mode control eliminates the doubl e pole effect of the output l&c filter. it greatly simp lifies the compensation loop design. with peak current mode control, the buck power stage can be simplified to be a one-pole and one-zero system in frequency domain. the pole is dominant pole can be calculated by: the zero is a esr zero due to output capacitor and its esr. it is can be calculated by: where; c o is the output filter capacitor, r l is load resistor value, and esr co is the equivalent series resistance of output capacitor. the compensation design is ac tually to shape the con- verter control loop transfer function to get desired gain and phase. several different types of compensation net- work can be used for the aoz1031a. for most cases, a series capacitor and resistor network connected to the comp pin sets the pole-zero and is adequate for a stable high-bandwidth control loop. in the aoz1031a, fb pin and comp pin are the inverting input and the output of internal error amplifier. a series r and c compensation network connected to comp pro- vides one pole and one zero. the pole is: where; g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, g vea is the error amplifier voltage gain, which is 500 v/v, and c 2 is compensation capacitor in figure 1. the zero given by the external compensation network, capacitor c 2 and resistor r 3 , is located at: to design the compensation circuit, a target crossover frequency f c for close loop must be selected. the system crossover frequency is where control loop has unity gain. the crossover is the also called the converter bandwidth. generally a higher bandwidth means faster response to load transient. however, the bandwidth should not be too high because of system stab ility concern. when design- ing the compensation loop, converter stability under all line and load condition must be considered. usually, it is recommended to set the bandwidth to be equal or less than 1/10 of switching frequency. the aoz1031a operates at a frequency range from 500khz to 700khz. it is recommended to choose a crossover fre- quency equal or less than 40khz. the strategy for choosing r c and c c is to set the cross over frequency with r c and set the compensator zero with c c . using selected crossover frequency, f c , to calcu- late r c : where; f c is desired crossover frequency. for best performance, f c is set to be about 1/10 of switching frequency, v fb is 0.8v, g ea is the error amplifier transconductance, which is 200 x 10 -6 a/v, and g cs is the current sense circuit transconductance, which is 6.68 a/v. the compensation capacitor c c and resistor r c together make a zero. this zero is put somewhere close to the dominate pole f p1 but lower than 1/5 of selected cross- over frequency. c c can is selected by: i co_rms i l 12 ---------- = f p 1 1 2 c o r l ---------------------------------- - = f z 1 1 2 c o esr co ------------------------------------------------ = f p 2 g ea 2 c c g vea ------------------------------------------ - = f z 2 1 2 c c r c ----------------------------------- = f c 40 khz = r c f c v o v fb ---------- 2 c 2 g ea g cs ----------------------------- - = c c 1.5 2 r c f p 1 ----------------------------------- =
AOZ1031AI rev. 1.6 march 2010 www.aosmd.com page 11 of 15 equation above can also be simplified to: an easy-to-use application software which helps to design and simulate the compensation loop can be found at www.aosmd.com . thermal management and layout consideration in the aoz1031a buck regulator circuit, high pulsing cur- rent flows through two circuit loops. the first loop starts from the input capacitors, to the vin pin, to the lx pins, to the filter inductor, to the output capacitor and load, and then return to the input capacitor through ground. current flows in the first loop when the high side switch is on. the second loop starts from indu ctor, to the output capacitors and load, to the low side nmosfet. current flows in the second loop when the low side nmosfet is on. in pcb layout, minimizing the two loops area reduces the noise of this circuit and improves efficiency. a ground plane is strongly recommended to connect input capaci- tor, output capacitor, and pgnd pin of the aoz1031a. in the aoz1031a buck regulator circuit, the major power dissipating components are the aoz1031a and the out- put inductor. the total power dissipation of converter cir- cuit can be measured by input power minus output power. the power dissipation of inductor can be approximately calculated by output curr ent and dcr of inductor. the actual junction temperature can be calculated with power dissipation in the aoz1031a and thermal imped- ance from junction to ambient. the maximum junction temperature of aoz1031a is 150 c, which limits the maximum load current capability. please see the thermal de-rating curves for maximum load current of the aoz1031a under different ambient temperature. the thermal performance of the aoz1031a is strongly affected by the pcb layout. extra care should be taken by users during design process to ensure that the ic will operate under the recommended environmental condi- tions. the aoz1031a is standard so-8 package. several lay- out tips are listed below for the best electric and thermal performance. fi gure 3 on the next page illustrates a pcb layout example of aoz1031a. 1. the lx pins are connected to internal pfet and nfet drains. they are low resistance thermal con- duction path and most noisy switching node. con- nected a large copper plane to lx pin to help thermal dissipation. 2. do not use thermal relief connection to the vin and the pgnd pin. pour a maximized copper area to the pgnd pin and the vin pin to help thermal dissipa- tion. 3. input capacitor should be connected to the vin pin and the pgnd pin as close as possible. 4. a ground plane is preferred. if a ground plane is not used, separate pgnd from agnd and connect them only at one point to avoid the pgnd pin noise cou- pling to the agnd pin. 5. make the current trace from lx pins to l to co to the pgnd as short as possible. 6. pour copper plane on all unused board area and connect it to stable dc nodes, like vin, gnd or vout. 7. keep sensitive signal trace far away form the lx pins. c c c o r l r c --------------------- = p total_loss v in i in v o i o ? = p inductor_loss i o 2 r inductor 1.1 = t junction p total_loss p inductor_loss ? () ja =
AOZ1031AI rev. 1.6 march 2010 www.aosmd.com page 12 of 15 figure 3. aoz1031a (so-8) pcb layout
rev. 1.6 march 2010 www.aosmd.com page 13 of 15 AOZ1031AI package dimensions, so-8l notes: 1. all dimensions are in millimeters. 2. dimensions are inclusive of plating 3. package body sizes exclude mold flash and gate burrs. mold flash at the non-lead sides should be less than 6 mils. 4. dimension l is measured in gauge plane. 5. controlling dimension is millimeter, converted inch dimensions are not necessarily exact. symbols a a1 a2 b c d e1 e e h l dimensions in millimeters min. 1.35 0.10 1.25 0.31 0.17 4.80 3.80 5.80 0.25 0.40 0 d c l h x 45 7 (4x) b 2.20 5.74 0.80 unit: mm 1.27 a1 a2 a 0.1 gauge plane seating plane 0.25 e 8 1 e1 e nom. 1.65 ? 1.50 ? ? 4.90 3.90 1.27 bsc 6.00 ? ? ? max. 1.75 0.25 1.65 0.51 0.25 5.00 4.00 6.20 0.50 1.27 8 symbols a a1 a2 b c d e1 e e h l dimensions in inches min. 0.053 0.004 0.049 0.012 0.007 0.189 0.150 0.228 0.010 0.016 0 nom. 0.065 ? 0.059 ? ? 0.193 0.154 0.050 bsc 0.236 ? ? ? max. 0.069 0.010 0.065 0.020 0.010 0.197 0.157 0.244 0.020 0.050 8
rev. 1.6 march 2010 www.aosmd.com page 14 of 15 AOZ1031AI tape and reel dimensions so- 8 carrier tape so- 8 reel so- 8 tape leader/trailer & orientation tape size 12mm reel size ?330 m ?330.00 0.50 packa g e so- 8 (12mm) a0 6.40 0.10 b0 5.20 0.10 k0 2.10 0.10 d0 1.60 0.10 d1 1.50 0.10 e 12.00 0.10 e1 1.75 0.10 e2 5.50 0.10 p0 8 .00 0.10 p1 4.00 0.10 p2 2.00 0.10 t 0.25 0.10 n ?97.00 0.10 k0 unit: mm b0 g m w 1 s k h n w v r trailer tape 300mm min. or 75 empty pockets components tape orientation in pocket leader tape 500mm min. or 125 empty pockets a0 p1 p2 see n ote 5 see n ote 3 see n ote 3 feeding direction p0 e2 e1 e d0 t d1 w 13.00 0.30 w1 17.40 1.00 h ?13.00 +0.50/-0.20 k 10.60 s 2.00 0.50 g ? r ? v ?
rev. 1.6 march 2010 www.aosmd.com page 15 of 15 AOZ1031AI aoz1031 package marking z1031ai fay part number code assembly lot code year & week code wlt fab & assembly location as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provid ed in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. this datasheet contains preliminary data; supplementary data may be published at a later date. alpha & omega semiconductor reserves the right to make changes at any time without notice. life support policy alpha & omega semiconductor products ar e not authorized for use as critical components in life supp ort devices or systems.

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